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19-1100; Rev 0; 6/96
KIT ATION EVALU LE VAILAB A
8-Bit, 300Msps Flash ADC
____________________________Features
o o o o o o Metastable Errors Reduced to 1LSB 10pF Input Capacitance 210MHz Input Bandwidth 300Msps Conversion Rate 2.2W Typical Power Dissipation Single -5.2V Supply
_______________General Description
The MAX1125 is a monolithic, flash analog-to-digital converter (ADC) capable of digitizing a 2V analog input signal into 8-bit digital words at a typical 300Msps update rate. For most applications, no external sample-and-hold is required for accurate conversion due to the device's narrow aperture time, wide bandwidth, and low input capacitance. A single standard -5.2V power supply is required to operate the MAX1125, with nominal 2.2W power dissipation. A special decoding scheme reduces metastable errors to 1LSB. The part is packaged in a 42-pin ceramic sidebraze that is pin compatible with the CX20116 and CX41396D. The surface-mount 44-pin CERQUAD package allows access to additional reference ladder taps, an overrange bit, and a data-ready output. The pincompatible 150Msps MAX1114 is also available.
MAX1125
______________Ordering Information
PART TEMP. RANGE PIN-PACKAGE INL (LSBs) 0.75 1 0.75 1 MAX1125AIDO -20C to +85C 42 Ceramic SB MAX1125BIDO -20C to +85C 42 Ceramic SB MAX1125AIBH -20C to +85C 44 CERQUAD MAX1125BIBH -20C to +85C 44 CERQUAD
Functional Diagram appears at end of data sheet.
________________________Applications
Digital Oscilloscopes Transient Capture Radar, EW, ECM Direct RF Down-Conversion Medical Electronics Ultrasound, CAT Instrumentation
____Pin Configurations (continued)
TOP VIEW
VEE N.C. LINV VEE 1 2 3 4 5 6 7 8 9 42 N.C. 41 VRTF 40 N.C.
_________________Pin Configurations
D8 (MSB) D0 (LSB) DREADY
MAX1125
39 VEE 38 VEE 37 N.C. 36 N.C. 35 AGND 34 VIN 33 AGND 32 VR2 31 AGND 30 VIN 29 AGND 28 N.C. 27 N.C. 26 VEE 25 VEE 24 N.C. 23 VRBF 22 N.C.
AGND DGND
TOP VIEW
DGND
DO (LSB) D1 D2
D7
D6
D5
D4
D3
39
D2
38
42
44
43
41
40
D1
37
36
35
34
D3 10 DGND AGND VEE MINV CLK CLK VEE AGND AGND
1 2 3 4 5 6 7 8 9 33 AGND 32 VEE 31 LINV 30 N.C.
D4 11 D5 12 D6 13 D7 (MSB) 14 DGND 15 AGND 16 VEE 17 MINV 18 N.C. 19 CLK 20
MAX1125
29 DRINV 28 N.C. 27 VEE 26 AGND 25 AGND 24 VRTS 23 VRTF
VRBS 10 VRBF 11
AGND 20
AGND 14
AGND 18
AGND 16
VR3 21
VEE 12
VR1 13
VR2 17
VIN 19
VIN 15
VEE 22
CLK 21
Ceramic SB
CERQUAD
________________________________________________________________ Maxim Integrated Products
1
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8-Bit, 300Msps Flash ADC MAX1125
ABSOLUTE MAXIMUM RATINGS
Negative Supply Voltage (VEE TO GND) ..............-7.0V to +0.5V Ground Voltage Differential ...................................-0.5V to +0.5V Analog Input Voltage ...............................................VEE to +0.5V Reference Input Voltage ..........................................VEE to +0.5V Digital Input Voltage ................................................VEE to +0.5V Reference Current VRTF to VRBF ........................................25mA Digital Output Current ...........................................0mA to -30mA Operating Temperature Range ...........................-25C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10sec). ............................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VEE = -5.2V, RSOURCE = 50, VRBF = -2.00V, VR2 = -1.00V, VRTF = 0.00V, fCLK = 150MHz, 50% Duty Cycle, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER DC ACCURACY Integral Linearity Differential Linearity No Missing Codes ANALOG INPUT Offset Error VRT Offset Error VRB Input Voltage Range Input Capacitance Input Resistance Input Current Input Slew Rate Large Signal Bandwidth Small Signal Bandwidth REFERENCE INPUT Ladder Resistance Reference Bandwidth TIMING CHARACTERISTICS Maximum Sample Rate Clock to Data Delay Output Delay TEMPCO CLK-to-Data Ready Delay (tD) Aperture Jitter Acquisition Time VI V V V V V 250 300 2.4 2 2.0 5 1.5 250 300 2.4 2 2.0 5 1.5 Msps ns ps/C ns ps ns VI V 100 200 10 300 100 200 10 300 MHz VIN = full scale IN = 500mVp-p Over full input range IV IV VI V V VI V V V -30 -30 -2.0 10 15 250 1,000 210 335 500 +30 +30 0.0 -30 -30 -2.0 10 15 250 1,000 210 335 500 +30 +30 0.0 mV mV V pF k A V/s MHz MHz VI VI -0.75 -0.75 Guaranteed 0.60 +0.75 +0.75 -0.95 -0.95 Guaranteed 0.80 +0.95 +0.95 LSB LSB CONDITIONS TEST LEVEL MIN MAX1125A TYP MAX MIN MAX1125B TYP MAX UNITS
2
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8-Bit, 300Msps Flash ADC
ELECTRICAL CHARACTERISTICS (continued)
(VEE = -5.2V, RSOURCE = 50, VRBF = -2.00V, VR2 = -1.00V, VRTF = 0.00V, fCLK = 150MHz, 50% Duty Cycle, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER DYNAMIC PERFORMANCE Signal-to-Noise Ratio Total Harmonic Distortion Signal-to-Noise and Distortion (SINAD) DIGITAL INPUTS Digital Input High Voltage (MINV, LINV) Digital Input Low Voltage (MINV, LINV) Clock Synchronous Input Currents Clock Low Width, TPWL Clock High Width, TPWH DIGITAL OUTPUTS Digital Output High Voltage Digital Output Low Voltage Supply Current Power Dissipation TEST LEVEL CODES All electrical characteristics are subject to the following conditions: All parameters having min/max specifications are guaranteed. The Test Level column indicates the specific device testing actually performed during production and Quality Assurance inspection. Any blank section in the data column indicates that the specification is not tested at the specified condition. Unless otherwise noted, all tests are pulsed; therefore, Tj = TC = TA. 50 to -2V 50 to -2V TA = +25 C TA = +25 C VI VI V I I TEST LEVEL I II III IV V VI 2.4 425 2.2 TEST PROCEDURE 100% production tested at the specified temperature. 100% production tested at TA = +25C, and sample tested at the specified temperatures. QA sample tested only at the specified temperatures. Parameter is guaranteed (but not tested) by design and characterization data. Parameter is a typical value for information purposes only. 100% production tested at TA = +25C. Parameter is guaranteed over specified temperature range. 550 2.9 -1.1 -1.5 2.4 425 2.2 550 2.9 -1.1 -1.5 V V ns mA W VI VI V VI VI 2 2 -1.1 -2.0 40 1.8 1.8 2 2 -0.7 -1.5 -1.1 -2.0 40 1.8 1.8 -0.7 -1.5 V V A ns ns FIN = 3.58MHz FIN = 100MHz FIN = 3.58MHz FIN = 100MHz FIN = 3.58MHz FIN = 100MHz VI VI VI VI VI VI 45 39 -48 -40 44 37 47 42 -52 -43 46 39 44 38 -46 -39 42 35 46 41 -50 -42 44 37 dB dB dB CONDITIONS TEST LEVEL MAX1114A TYP MAX MAX1114B TYP MAX UNITS
MAX1125
MIN
MIN
POWER-SUPPLY REQUIREMENTS
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8-Bit, 300Msps Flash ADC MAX1125
__________________________________________Typical Operating Characteristics
SIGNAL-TO-NOISE RATIO vs. INPUT FREQUENCY
MAX1125 -01
TOTAL HARMONIC DISTORTION vs. INPUT FREQUENCY
70 65 60 THD (dB) 55 50 45 40 35 30 1 10 INPUT FREQUENCY (MHz) 100 fs = 250Msps
MAX1125 -02
52 50 48 46 SNR (dB) 44 42 40 38 36 34 1
75
fs = 250Msps
10 INPUT FREQUENCY (MHz)
100
SIGNAL-TO-NOISE AND DISTORTION vs. INPUT FREQUENCY
50 48 SNR, THD, SINAD (dB) 46 SINAD (dB) 44 42 40 38 36 34 1 10 INPUT FREQUENCY (MHz) 100 30 -40 -20 fs = 250Msps
MAX1125 -03
SNR, THD, SINAD vs. TEMPERATURE
fs = 250Msps fIN = 100MHz 45 THD 40 SINAD 35 SNR
MAX1125 -04
52
50
0
20
40
60
80
TEMPERATURE (C)
4
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8-Bit, 300Msps Flash ADC
______________________________________________________________Pin Description
PIN NAME Ceramic SB 1, 4, 17, 25, 26, 38, 39 2, 19, 22, 24, 27, 28, 36, 37, 40, 42 3 5, 16, 29, 31, 33, 35 6, 15 7 8-13 14 18 -- 20 21 -- 23 30, 34 -- 32 -- 41 -- -- -- CERQUAD 3, 7, 12, 22, 27, 32 28, 30 31 2, 8, 9, 14, 16, 18, 20, 25, 26, 33 1, 34 36 37-42 43 4 44 5 6 10 11 15, 19 13 17 21 23 24 29 35 VEE N.C. LINV AGND DGND D0 D1-D6 D7 MINV D8 CLK CLK VRBS VRBF VIN VR1 VR2 VR3 VRTF VRTS DRINV DREADY Negative Analog Supply (nominally -5.2V) No Connect. Not internally connected. D0-D6 Output Inversion Control Analog Ground Digital Ground Digital Data Output (LSB) Digital Data Output Digital Data Output (MSB) D7 Output Inversion Control Overrange Output Inverse ECL Clock Input Pin ECL Clock Input Pin Reference Voltage Bottom, Sense Reference Voltage Bottom, Force Analog Input. Can be connected to the input signal or used as a sense. Reference Voltage Tap 1 (typically -1.5V) Reference Voltage Tap 2 (typically -1V) Reference Voltage Tap 3 (typically -0.5V) Reference Voltage Top, Force Reference Voltage Top, Sense Data-Ready Inverse Data-Ready Output FUNCTION
MAX1125
_______________Detailed Description
The MAX1125 is a 300Msps, monolithic, 8-bit parallel flash analog-to-digital converter (ADC) with an analog bandwidth of over 200MHz. A major advance over previous flash converters is the inclusion of 256 input preamplifiers between the reference ladder and input comparators. (See Functional Diagram.) This feature not only reduces clock-transient kickback to the input and reference ladder due to a low AC beta, but also
reduces the effect of the dynamic state of the input signal on the latching characteristics of the input comparators. The preamplifiers act as buffers and stabilize the input capacitance so it remains constant for varying input voltages and frequencies, making the part easier to drive than previous flash converters. The MAX1125 incorporates a special decoding scheme that reduces metastable errors (sparkle codes or flyers) to a maximum of 1LSB.
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5
8-Bit, 300Msps Flash ADC MAX1125
The MAX1125 has true differential analog and digital data paths from the preamplifiers to the output buffers (Current-Mode Logic) for reducing potential missing codes while rejecting common-mode noise. Careful layout of the analog circuitry reduces signature errors. Every comparator also has a clock buffer to reduce differential delays and to improve signal-tonoise ratio. The output-drive capability of the device can provide full ECL swings into 50 loads.
Clock Inputs CLK, CLK
The clock inputs are designed to be driven differentially with ECL levels. Because CLK is internally biased to -1.3V, the clock may be driven single-ended (Figure 5). CLK may be left open, but a 0.01F bypass capacitor from CLK to AGND is recommended. NOTE: System performance may be degraded due to increased noise or jitter.
Output Logic Control MINV, LINV
These are ECL-compatible digital controls for changing the output code from straight binary to two's complement, etc. (Table 1 and Figure 4). Both MINV and LINV are in the logic low (0) state when left open. The high state can be obtained by tying to AGND through a diode or 3.9k resistor.
___________Typical Interface Circuit
Figure 1 shows the typical interface circuit. The MAX1125 is relatively easy to apply depending on the accuracy needed. Wire-wrap may be employed with careful point-to-point ground connections if desired, but a double-sided PC board with a ground plane on the component side, separated into digital and analog sections, gives the best performance. The converter is bonded-out to place the digital pins on the left side of the package and the analog pins on the right side. Additionally, an RF bead connection through a single point from the analog to digital ground planes reduces ground noise pickup. Figure 2 (CERQUAD package only) shows the most elaborate method of achieving the least error by correcting for integral nonlinearity, input induced distortion, and power-supply/ground noise. It uses external reference ladder tap connections, an input buffer, and supply decoupling. The function of each pin and external connections to other components is as follows:
Table 1. Output Coding
MINV LINV 0V . . . . VIN . . . . . . -2V 0 0 111...11 111...10 . . . 100...00 011...11 . . . 000...01 000...00 1: VIH, VOH 0 1 100...00 100...01 . . . 111...11 000...00 . . . 011...10 011...11 1 0 011...11 011...10 . . . 000...00 111...11 . . . 100...01 100...00 1 1 000...00 000...01 . . . 011...11 100...00 . . . 111...10 111...11
VEE, AGND, DGND
V EE is the supply pin with AGND as ground for the device. The power-supply pins should be bypassed as close to the device as possible with at least a 0.01F ceramic capacitor. A 1F tantalum should also be used for low-frequency suppression. DGND is the ground for the ECL outputs and should be referenced to the output pulldown voltage and bypassed as shown in Figure 1.
0: VIL, VOL
Digital Outputs D0 to D7
The digital outputs can drive ECL levels into 50 when pulled down to -2V. When pulled down to -5.2V, the outputs can drive 150 to 1k loads.
Analog Input VIN
There are two analog input pins that are tied to the same point internally. Either one may be used as an analog input sense and the other for input force. This is convenient for testing the source signal to see if there is sufficient drive capability. The pins can also be tied together and driven by the same source. The MAX1125 is superior to similar devices due to a preamplifier stage before the comparators (Figure 4). This makes the device easier to drive because it has constant capacitance and induces less slew-rate distortion. An optional input buffer may be used.
Reference Inputs VRBF, VR2, VRTF
There are two reference inputs and one external reference voltage tap. These are -2V (VRBF), mid-tap (VR2) and AGND (VRTF). The reference pins can be driven as shown in Figure 1. VR2 should be bypassed to AGND for further noise suppression.
Reference Inputs VRBF, VRBS, VR1, VR2, VR3, VRTF, VRTS (CERQUAD package only)
These are five external reference voltage taps from -2V (VRBF) to AGND (VRTF) that can be used to control integral linearity over temperature. The taps can be driven by
6
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8-Bit, 300Msps Flash ADC
op amps (Figure 2). These voltage level inputs can be bypassed to AGND for further noise suppression, if so desired. VRB and VRT have force and sense pins for monitoring the top and bottom voltage references. tive input of each preamplifier/comparator pair. An analog input voltage applied at VIN is connected to the negative inputs of each preamplifier/comparator pair. The comparator states are then clocked through each comparator's individual clock buffer. When CLK is low, the comparators' master, or input stage, compares the analog input voltage to the respective reference voltage. When CLK changes from low to high, the comparators are latched to the state prior to the clock transition and output logic codes in sequence from the top comparators, closest to VRTF (0V), down to the point where the magnitude of the input signal changes sign (thermometer code). The output of each comparator is then registered into four 64-to-6 bit decoders when CLK changes from high to low. At the output of the decoders is a set of four 7-bit latches that are enabled (track) when CLK changes from high to low. From here, the outputs of the latches are coded into 6 LSBs from 4 columns and 4 columns are coded into 2 MSBs. Next are the MINV and LINV controls for output inversions that consist of a set of eight XOR gates. Finally, 8 ECL output latches and buffers are used to drive the external loads. The conversion takes one clock cycle from the input to the data outputs.
MAX1125
Not Connected (N.C.)
All N.C. pins should be tied to DGND on the left side of the package and to AGND on the right side of the package.
Data Ready and Data Ready Inverse DREADY, DRINV (CERQUAD package only)
The data-ready pin is a flag that goes high or low at the output when data is valid or ready to be received. It is essentially a delay line that accounts for the time necessary for information to be clocked through the MAX1125's decoders and latches. This function is useful for interfacing with high-speed memory. Using the data-ready output to latch the output data ensures minimum setup and hold times. DRINV is a data-ready inverse control pin (Figure 3).
Overrange Input D8 (CERQUAD package only)
When the MAX1125 is in an overrange state, D8 goes high, and all data outputs go high as well. This makes it possible to include the MAX1125 in higher resolution systems.
_________________Evaluation Boards
The MAX1114/MAX1125 evaluation kit (EV kit) demonstrates the full performance of the MAX1125. This board includes a voltage reference circuit, clock driver circuit, output data latches and an on-board reconstruction of the digital data. A separate data sheet describing the operation of this board is also available. Contact the factory for price and delivery.
Operation
The MAX1125 has 256 preamp/comparator pairs that are each supplied with the voltage from VRTF to VRBF divided equally by the resistive ladder as shown in the Functional Diagram. This voltage is applied to the posi-
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7
8-Bit, 300Msps Flash ADC MAX1125
ANALOG INPUT CAN BE EITHER FORCE OR SENSE. VRTF VIN PREAMP COMPARATOR 256 CLOCK BUFFER 255 = AGND = DGND L 0.01F VEE -5.2V LINV MINV
OPTIONAL BUFFER
152
D7 (MSB) 151 D6 128 VR2 0.01F 127 D4 256-BIT TO 8-BIT ENCODER ECL LATCHES AND BUFFERS
D5
64
D3
D2 63
D1 2 D0 (LSB) VREF -2V 10 TO 25 OP07 1 VRBF 0.01F VIN 100116 CONVERT 50 50 CLK CLK 2
MAX1125
50 x 8
*
-2V (ANALOG)
0.01F
0.01F
VEE -5.2V
0.01F
-2V (DIGITAL)
Figure 1. Typical Interface Circuit 1
8 _______________________________________________________________________________________
8-Bit, 300Msps Flash ADC MAX1125
OPTIONAL BUFFER
*
DGND VRTF VRTS VIN LINV MINV L AGND 0.01F VEE -5.2V
10 TO 25 U1
0.01F
PREAMP COMPARATOR 256 CLOCK BUFFER 255
*ANALOG INPUT (FORCE) **ANALOG INPUT (SENSE)
OVERRANGE D8
1k, 0.1% 10 TO 25 U2 D7 (MSB) 151 0.01F 1k, 0.1% 10 TO 25 U3 128 VR2 256-BIT TO 8-BIT ENCODER ECL LATCHES AND BUFFERS D6 152 VR3
NOTE: U1-U5 ARE OP07 OR EQUIVALENT, LOW-NOISE, LOW-OFFSET AMPLIFIERS. 1k, 0.1%
D5
0.01F
127 D4
10 TO 25 U4
64 VR1
D3
D2 0.01F 63
D1 1k, 0.1% VREF -2V U5 2 D0 (LSB) 10 TO 25 VRBF VRBS 0.01F 100116 CONVERT 50 -2V (ANALOG) 50 CLK CLK 1
MAX1125
2 VIN VEE VEE -5.2V AGND
DRINV DREADY 50 x 10
**
0.01F
0.01F
0.01F
-2V -2V (DIGITAL)
0.01F
Figure 2. Typical Interface Circuit 2 (CERQUAD package only)
_______________________________________________________________________________________ 9
8-Bit, 300Msps Flash ADC MAX1125
N+2 ANALOG INPUT VIN Tpw1 CLOCK CLK CLK Tpw0 N N+1
MASTER COMPARATOR OUTPUT SLAVE INTERNAL TIMING N-1 tD N
N+1
6-BIT LATCH OUTPUT
8-BIT LATCH OUTPUT
DATA OUTPUT D0-D7 OVERRANGE D8 DREADY
TIMING FOR CERQUAD PACKAGE ONLY
Figure 3. Timing Diagram
AGND DGND 10k MINV LINV -1.3V DATA OUT AGND
VIN
AGND VR
16k VEE VEE
INPUT CIRCUIT
OUTPUT CIRCUIT
MINV, LINV INPUT CIRCUIT
Figure 4. Subcircuit Schematics
10 ______________________________________________________________________________________
8-Bit, 300Msps Flash ADC MAX1125
AGND
CLK 13k CLK
-1.3V
13k VEE
Figure 5. Clock Input
VEE 1N4736 -2V R4 VREF R4 R1 R1 R1 R1 R1 R1 R1 R1
R3
VRBF
VEE
D0 D1
R2 VIN VIN
D2
MAX1125
D3 D4 D5
CLK CLK
R2 CLK CLK R2 DGND AGND VRTF
D6 D7 LINV MINV R2
R1 = 50 1/4 Watt CC 5% R2 = 1k 1/4 Watt CC 5% R3 = 6.5 1/4 Watt CC 5% R4 = 6.5 1/2 Watt CC 5% VREF = -2.00V VEE = -6.6V
-2V
Figure 6. Burn-In Circuit (Ceramic SB package only)
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8-Bit, 300Msps Flash ADC MAX1125
_________________________________________________________Functional Diagram
ANALOG INPUT (FORCE OR SENSE) AGND DGND VEE LINV MINV
VRTS VRTF PREAMP COMPARATOR 256 CLOCK BUFFER 255 D7 (MSB)
MAX1125
DRINV
DREADY
VR3
152
OVERRANGE
151
D7 (MSB)
D6 128 VR2 256-BIT TO 8-BIT ENCODER ECL LATCHES AND BUFFERS
D5
127 D4 D6 64 D5 D4 VR1 63 D3 D2 D1 2 D1 D0 (LSB) D0 (LSB) D2
D3
1 VRBE VRBS CONVERT CLK CLK 2
THESE FUNCTIONS ARE AVAILABLE IN THE CERQUAD PACKAGE ONLY. VEE AGND
ANALOG INPUT (FORCE OR SENSE)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 __________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600 (c) 1996 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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